1. Field of the Invention
The present invention generally relates to carry adders and more particularly to carry select adders which generate two pairs of candidate carry-out signals and include selectors for choosing one candidate carry-out signal from each of the two pairs, depending upon a carry-in signal.
2. Description of the Related Art
Adders are used to perform mathematical functions, increment counters and perform address calculations. Many recent designs use dynamic logic to speed up the adders. Dynamic logic introduces an entirely new set of requirement to the design of adders, such as the need for pre-charge time and the gating of inputs to the dynamic logic circuits. Further, there are problems associated with the increasing power noise and the power dissipation associated with dynamic logic circuits.
There are many different approaches to the design of adders. Dynamic adders are the fastest but introduce many undesirable design considerations. In static adders many trade-offs are made between circuit complexity and the total number of logic stages in the critical path.
Two common adders are the carry look ahead adder and the carry select adder. The carry select adder trades circuit redundancy and the speed of the selectors for a larger number of delay stages. A carry look ahead adder generally has a more complex logic structure and a larger fanout but has fewer delay stages. The shortest static adder delay occurs with the carry look ahead design, but some carry select adders, with simpler and denser designs, have performance levels close to the carry look ahead adder.
The carry-select adder operates as follows. Two additions are performed in parallel. One presumes that the carry-in will be "0" and the other presumes that the carry-in will be "1". When the actual carry-in becomes known, the carry select adder selects the result of the addition operation which corresponds to the actual carry-in. By precalculating alternative addition results, the speed of the adder is increased. A typical carry select adder is shown in U.S. Pat. No. 5,487,025 to Partovi et al., and U.S. Pat. No. 4,982,357 to Bechade, which are incorporated herein by reference.
A conventional 16-bit carry select adder is shown in FIG. 8. The carry select adder shown in FIG. 8 is used to add a 16-bit value A to another 16-bit value B. A 4-bit adder 810 receives the least significant four bits A.sub.0-3, B.sub.0-3 of the two 16-bits to be summed. Adder 810 adds the four bits and produces a sum output S 0.sub.0-3 and a carry-out C0.sub.0-3 based on a presumed carry-in of "0" C.sub.0.
Simultaneously, a 4-bit adder 811 performs the same operation as adder 810 except that adder 811 operates based on a presumed carry-in of "1" C.sub.1 and outputs a sum output S1.sub.0-3 and a carry-out C1.sub.0-3.
Both adders 810, 811 output to a value selector 812 and a carry selector 813. The value selector 812 chooses between the two sum outputs S0.sub.0-3, S1.sub.0-3, based on an actual carry-in C.sub.in, and outputs a sum output S.sub.0-3. Similarly, the carry selector 813 chooses between the two carry-outs C.sub.0-3, C1.sub.0-3 based on an actual carry-in C.sub.in and outputs a carry-out C.sub.0-3. Therefore, the carry selector will choose C0.sub.0-3 as the actual carry-out. The two parallel 4-bit adders 810, 811 and the selectors 812, 813 are sometimes called a carry chain.
The next most significant four bits, A.sub.4-7, B.sub.4-7 are similarly summed in parallel (i.e., simultaneously) by two 4-bit adders 820 and 821. Adder 820 receives a presumed carry-in of "0" C.sub.0 and outputs a first potential sum S0.sub.4-7 and carry-out C0.sub.4-7 based on the carry-in being "0". Adder 821 receives a presumed carry-in of "1" C.sub.1 and outputs a first potential sum S1.sub.4-7 and carry-out C1.sub.4-7 based on the carry-in being "1".
A value selector 822 receives the actual carry-out C.sub.0-3 from the carry selector 813 as a true (or actual) carry-in and selects between the outputs S0.sub.4-7 and S1.sub.4-7 based on whether the carry-out from carry selector 113 is "1" or "0". The value selector 822 outputs a true sum output S.sub.4-7. Similarly, a carry selector 823 receives the true carry-out C.sub.0-3 from carry selector 813 as a true carry-in and selects between carry-out C.sub.4-7 and carry-out C1.sub.4-7 based on whether the true carry-out from carry selector 813 is "1" or "0". Carry selector 823 outputs a true carry-out C.sub.4-7.
Similarly, the next carry chains add the higher order bits. Adders 830, 831 and 840, 841 sum the next most significant bits A.sub.8-11, B.sub.8-11 and A.sub.12-15, B.sub.12-15 in parallel and output first potential sums S0.sub.8-11, S1.sub.8-11, S0.sub.12-15 and S1.sub.12-15 based on a presumed carry-in of "0" and "1", respectively. Value selectors 832 and 842 select the true sum outputs S.sub.8-11, S.sub.12-15 from the potential sum outputs S0.sub.8-11, S1.sub.8-11, S0.sub.12-15 and S1.sub.12-15 based on whether the actual carry-out C.sub.4-7, C.sub.8-11 from the previous carry selectors 823, 833 are "0" or "1". Carry selectors 833, 843 similarly select from the respective carry-outs C0.sub.8-11, C1.sub.8-11, C0.sub.12-15 and C1.sub.12-15 also based on whether the actual carry-out C.sub.4-7, C.sub.8-11 from the previous carry selectors 823, 833 are "0" or "1".
Carry select adders are able to decrease the time required to sum values because each carry chain operates in parallel (i.e., simultaneously). Once the carry chain for the least significant bits (i.e., 0-3) completes a sum operation and outputs a true carry-out C.sub.0-3, the value selectors 822, 832 and 842 and carry selectors 823, 833 and 843 merely select between the candidate outputs which have been previously calculated by the adder units based on the actual carry-out of the previous carry selector.
However, conventional carry select adders require a large amount of carry selectors (i.e., one carry selector per carry chain) which increases the delay of the carry select adder because an additional delay is associated with each carry selector.